1. Introduction
Imagine arriving in a new area / national park / foreign land which is known for its beautiful scenery, dense forests, and more — known as a place where even the natives could spend a lifetime and still have more to experience and learn. My mind’s eye has images of Grand Teton National Park and of New Zeland’s Middle Earth areas; I’ve heard that Tokyo gets a similar sentiment.
Welcome to the field of electronics.
Soon after what seems to be the entrance is a path which seems to branch into two different directions, analog and digital.
2. Bipolar transistor operation
Bipolar transistors are named as such because both electrons and holes participate in the device’s operation.
2.1. Useful tables
These tables are at the top for quick reference. 
BE junction  BC junction  Mode  Equations 

Reverse 
Reverse 
cutoff 
\( \begin{cases} i_C \approx 0 \\ i_B \approx 0 \end{cases} \) 
Forward 
Forward 
saturation 
\( \begin{cases} V_{BE} \approx 0.6 V \\ V_{CE} = V_{CE sat} \approx 0.1 \text{ to } 0.2 V \\ i_C \rightarrow \text{set by circuit conditions} \\ i_B \rightarrow \text{must be } > I_C/\beta \end{cases} \) 
Forward 
Reverse 
active 
\( \begin{cases} V_{BE} \approx 0.6 V \\ V_{CE} \rightarrow \text{set by circuit conditions} \\ i_C = \begin{cases} \alpha \, i_E \text{, or } \approx i_E\\ \beta \, i_B \\ I_S \exp \left( v_{BE} / V_T \right) \end{cases} \\ i_B = i_C / \beta \text{, or } \approx 0\\ \end{cases} \) 
Reverse 
Forward 
revactive 
(your transistor is in backwards) 
Term  Name  Definition 

\(\beta\) 
commonemitter current gain 
\(\beta = \dfrac{i_C}{i_B}\) 
\(\alpha\) 
commonbase current gain 
\(\alpha = \dfrac{i_C}{i_E}\) 
relationships 
\(\beta = \dfrac{\alpha}{1  \alpha}\\ \alpha = \dfrac{\beta}{\beta + 1}\) 

\(V_T\) 
thermal voltage 
\(\dfrac{k_B T}{q} \approx 26\,\mathrm{mV} \text{ at } 300\,\mathrm{K} \text{(room temp)}\) 
\(V_A\) 
Early voltage 
≈ 100 for discrete or 20 on IC 
[AoE] only mentions Early voltage and refers you to “Chapter 2x” of a (future) supplemental book. See Wikipedia: Early effect for a good description of this phenomenon. 
2.2. Structure and Physics
Figure Figure 1, “Cross section of a planar BJT” shows the side view of an npn BJT as it would be fabricated on a chip. The order of the threelayer sandwich determines the type (npn or pnp), while the doping level of the outer layers determines the Collector and Emitter terminal labels.
This is a note 
This is a tip 
This is important. 
This is a caution. 
This is a warning. 
2.3. Circuit Models
2.3.1. EbersMoll model
The EbersMoll model is accurate, useful, and therefore wellknown. It accounts for normal pn junction current flow and the “transistor action” current flow due to the shared middle region.
EbersMoll model for NPN The diode currents for Figure [EbersMoll model for NPN] are found in the normal way by their voltages:
Or, using KCL to find the terminal currents:
If we make the substitution \(I_S = \alpha_F I_{SE} = \alpha_R I_{SC}\), the equations become:
Summary to this point: we have a circuit model and set of equations describing the terminal currents given the terminal voltages for a bipolar transistor. There is no notion of operating mode here; this is one set of equations and the rest is plugandchug.
Take a minute to also see that the above equations apply equally well to the PNP in Figure [EbersMoll model for PNP].
2.3.2. GummelPoon model
The [GummelPoon] transistor model is an extension of the EbersMoll model to better match measurements and other effects. An important aspect is that it accounts for variation in \(\beta_{F,R}\) as device current changes. It is the default bipolar transistor model used in SPICE. A listing and brief description of the model’s parameters is at the Wikipedia page GummelPoon model.
2.3.3. EM approximations
Now we will start making some approximations to arrive at some simpler equations. The first is to drop the \(1\)’s. Doing this only introduces a significant error when the voltages are within a few multiples of \(V_T\), or less than about 100 mV at room temperature.
Now, make a few assumptions for the case of an NPN:

The collector is at an equal or higher potential than its emitter, \(v_C \ge v_E\).

The base is also at an equal or higher potential than the emitter, \(v_B \ge v_E\).
2.3.3.1. Cutoff
Imagine that the baseemitter voltage is near zero (a situation when we can’t ignore the \(1\), remember).
The first exponential term will be also near zero.
Also, the second exponential term’s \(v_{BC}\) will be near zero or negative.
This causes all of the currents to go to zero.
→ This is cutoff mode.
2.3.3.2. Active
Next imagine that the baseemitter voltage is increased until some reasonable amount of current flows through the forward biased baseemitter pn junction — \(v_{BE}\) will be around 0.6 V.
At the same time, the collector voltage is larger at some potential higher than the base, reverse biasing the basecollector junction.
The second exponential terms with \(v_{BC}\) will be nearly zero under these conditions and can be ignored.
→ This reduces to the equations for forward active mode.
Notice how the collector current is not influenced by the collector voltage.
2.3.3.3. Saturation
Finally, keep the baseemitter junction forward biased but keep increasing the current flowing into the base terminal by increasing \(v_{BE}\). The collector current will necessarily increase and, in a circuit, the effect will be that the collector’s voltage will decrease. See the Figure: Figure 5, “Saturation mode current flow” to look at this situation. The labels will help keep the current paths straight inside the transistor.
When the collector voltage is greater than the base voltage, diode Dbc
is reversebiased and therefore Iy is small enough to ignore.
This makes Ib = Ix and Ic = Iz, which holds until the base and collector voltages are equal.
[ slow down reading here ]
Now increase the base voltage so Iz increases. Remember the earlier relationship between base and collector currents: \(i_B = i_C / \beta_F\). This means that Ix and Iz are not independent and Ix = Iz / β as well.
Iz is increasing, which is lowering the collector voltage.
This causes diode Dbc
to become forward biased and start conducting (a little) current.
Iy works out to be \(\frac{I_S}{\beta_R} \,\exp\left(\frac{v_{BC}}{V_T}\right)\).
The collector voltage will end up at a voltage that satisfies KCL at the collector node to make Ic = Iz  Iy.
On the base side, you can see that Ib = Ix + Iy.
Is there any combination of \(\beta_F\) and \(\beta_R\) that allows the collector voltage to drop below the emitter voltage? 
The forward biased basecollector junction’s current simultaneously increases the base current and decreases the collector current from their expected values. Since the active mode simplification gives \(\beta_F = i_C / i_B\), we make a new version of β for saturation mode:
For a recap of saturation mode using this new \(\beta_{\text{sat}}\), remember that increasing \(i_B\) does not increase the collector terminal current Ic (it only increases both Iz and Iy).
You can see this effect by looking at Figure 16 on page 7 of ON Semiconductor’s datasheet for the 2N3904:

Each curve is for a constant collector current (set by an external constant current source).

During the vertical part of each curve, the transistor is in active mode. For example: on the 10 mA curve at \(v_{CE} = 1.0\,\mathrm{V}\), the base current is about \(80\,\mathrm{\mu A}\) making \(\beta_F \approx 125\) in that condition.

As base current increases, the collector voltage does not drop much and approaches 0.1 V.

Take Figure 16 and rotate it 90 degrees counterclockwise so the plot shows I vs. V.

Recall that the base voltage will only increase by 60 mV when the current increases by 10× → in other words consider the base voltage constant.

The voltage axis then basically plots the voltage across diode
Dbc
and its current. Do you see how the collector voltage drops a little to balance KCL at the collector node?

2.3.4. Shortcuts
There is a section at the end of most chapters in [CMOS VLSI] called “Pitfalls and Fallacies” which gives some hints on where it is easy to over or underthink an issue. A favorite that applies to this context is:
Using excessively complicated models for manual calculations:
Because models cannot be perfectly accurate, there is little value in using excessively complicated models, particularly for hand calculations. Simpler models give more insight on key tradeoffs and more rapid feedback during design.
The most important task is to figure out (a.k.a. guessthencheck) which mode the transistor is operating in. Remember that it is the state of the two pn junctions that determines the mode (forward or reverse). See the table Table 1, “Bipolar transistor modes” for a summary of these modes and the equations that are useful.
2.3.4.1. Example 1 analysis
For the figure Figure 6, “Example circuit with both collector and emitter resistors” use:

VB = 2.0 V

Vcc = 5.0 V

Rc = 1 kΩ

Re = 1 kΩ
Steps to quickly find the DC solution of this circuit:

Guess a mode → active.

Vb is known, so find Ve as 2.0  0.6 = 1.4 V.

The voltage across Re is now know, so find Ie as 1.4 V / 1 kΩ = 1.4 mA.

:beta: is large (and \(\alpha_F \approx 1\)), so just estimate Ic = Ie.

This is enough to find the (node) voltage at the collector as (5 V  1.4 mA × 1 kΩ) = (5  1.4) = 3.6 V.

That’s it! … wait, not until we check the mode:

Vc > Vb so
Q1
is indeed in _active_mode. 
Done.

Open up CircuitLab schematic cereexample and run a DC Simulation. Click on the nodes and device terminals to see the various node voltages and currents.
Notice that the simulator (which is SPICE underneath) reports the emitter current as negative. It turns out that SPICE defines all device currents as positive into the terminals. Also notice that the current changes sign when probing the current at either end of a resistor. Here also, SPICE uses polarized resistors, which is basically the + and  terminals are defined graphically before simulation. 
2.3.4.2. Example 2
Keep the same conditions as above, except change:

Rc ⇒ 10 kΩ
Not much changes on the emitter side of the circuit, so no need to redo the math.

Find Vc as (5 V  1.4 mA × 10 kΩ) = (5  14.0) = 9.0 V.

The first clue is a negative node voltage when there is no negative supply voltages.

The second is to check the operation mode:

Vb > Ve so the BE junction is forward biased. (no surprise since we forced this)

Vc < Vb so the BC junction is also forward biased. This violates our starting assumption of active mode. The solution is to redo the problem but assume a different mode (saturation).

Take another swig of coffee and start over. Oh wait, saturation only changes the collector side. All of the emitter side math stays the same.

Set Vce to 0.1 V according to the table.

Therefore Vc is 1.5 V.

Ic calculates to (5.0  1.5) / 10 kΩ = 0.35 mA.

If it is useful, we can use KCL to compute the base current as Ie  Ic = 1.05 mA.

The check is to see if base current is larger than what is predicted by \(\beta_F\). It is obviously larger than Ic / β, so the check passes.
Check that these numbers are close to what is simulated (which uses the Section 2.3.2, “GummelPoon model”) in the same CircuitLab schematic as the first example.
Finally, compute \(\beta_{\text{sat}} = 0.35 / 1.40 = 0.25\). This number is useful to see how deep into saturation the transistor is. Here, it is approximately oceanfloordeep saturation mode.
2.3.5. Rules of thumb
2.3.5.1. Ratio rules
Assuming two transistors are matched (their parameters such as I_{S} and temperature are exactly the same):

\(\dfrac{I_{C2}}{I_{C1}} = \exp\left(\dfrac{\Delta V_{BE}}{V_T}\right)\)

\(\Delta V_{BE} = V_T \ln\left( \dfrac{I_{C2}}{I_{C1}} \right)\)
2.3.5.2. Temperature dependence
[positive emphatic slang here], this is an important topic! IMNSHO, properly dealing with temperature dependence over the entire range of intended operational temperatures separates the professional from the amateur circuit designer.
It just works … always.
It may seem from Section 2.3.5.1, “Ratio rules” that temperature only shows up as \(V_T = \frac{k_B\,T}{q}\). Remember that the saturation current I_{S} is also a strong function of temperature (T^{4} !). The following relationships work well over nearly the entire electronics temperature ranges (very cold is interesting to Physicists, and much hotter and things start melting):
 Constant I_{C}


\(\Delta V_{BE} \approx 2.1 \,\mathrm{mV / ^\circ C}\)

\(\propto 1 / T\,\mathrm{(K)}\)

 Constant V_{BE}


\(\Delta I_C \approx 9\,\mathrm{\% / ^\circ C}\)

\(2\!\times I_C \text{ for } \Delta T = 8\,\mathrm{^\circ C}\)

3. Amplifier fundamentals
This chapter discusses the fundamentals of amplifiers and how we analyze and talk about them. These concepts apply to all amplifiers regardless of how they are constructed internally.
What makes this way of thinking about amplifiers so powerful is we can separate how the the amplifier is used in a larger system from how it is constructed internally. At any given time, a person is only concerned about one of these aspects and can therefore effectively not care about the other.
3.1. Prerequisites
We start with amplifiers which behave the same at all frequencies. This means that we are ignoring capacitors, inductors, and any frequencydependence of devices such as transistors.
[LEC] has a wellwritten tour of this material in Lessons in Electric Circuits: Volume 1  Direct Current, Chapters 1 through 10.
Most important to this discussion are the wonderful tools of ThÃ©venin (mostly) and Norton (some) equivalent circuits. You can find more discussion and worked examples at [CLbook]'s section Thevenin Equivalent and Norton Equivalent Circuits.

Analysis of circuits containing:

Ideal independent and dependent sources: VCVS, VCCS, CCVS, CCCS.

Resistors, capacitors, inductors.


Analysis techniques:

Equivalent circuts:

Thevenin / Norton



DC circuit analysis basics.

AC circuits
3.2. lower UPPER signal notation
Capitalization  Example  Meaning 

lower_{UPPER} 
\(v_{BE}\) 
total quantity, as measured by an oscilloscope with DC coupling 
UPPER_{UPPER} 
\(V_{BE}\) 
DC value (average) 
lower_{lower} 
\(v_{be}\) 
signal quantity, changes 
UPPER_{lower} 
\(V_{be}\) 
complexvalued phasor 
lower_{UPPER} = UPPER_{UPPER} + lower_{lower} 
\(v_{BE} = V_{BE} + v_{be}\) 
total signal is average + changes 
4. Bipolar transistor amplifiers
4.1. Tables and terminology
Symbol  Name  Definition 

\(g_m\) 
transconductance 
\(\dfrac{I_C}{V_T} = \dfrac{\alpha}{r_e}\) 
\(r_e\) 
intrinsic emitter resistance 
\(\dfrac{\alpha\, V_T}{I_C} = \dfrac{\alpha}{g_m}\) 
\(r_\pi\) 
intrinsic base resistance 
\(\dfrac{\beta\, V_T}{I_C} = \dfrac{\beta}{g_m}\) 
\(r_o\) 
intrinsic output resistance 
\(\dfrac{V_A}{I_C}\) 
\(\beta\) 
alternate 
\(g_m r_\pi\) 
\(A_0\) 
intrinsic voltage gain 
\(g_m r_o\) 
Symbol  Name 

\(Z_{\text{in}}\) 
Impedance looking into transistor input terminal. 
\(Z_{\text{out}}\) 
Impedance looking into transistor output terminal. 
\(A_{v\emptyset}\) 
Opencircuit voltage gain, no external load attached. 
\(Z_B\) 
Impedance at the base node looking away from the transistor. 
\(Z_E\) 
Impedance at the emitter node looking away from the transistor. 
\(Z_C\) 
Impedance at the collector node looking away from the transistor. 
In  Out  Name  \(\boldsymbol{Z_{\text{in}}}\)  \(\boldsymbol{Z_{\text{out}}}\)  VGain: \(\boldsymbol{A_{v\emptyset}}\) 

B 
E 
EF emitter follower / CC commoncollector 
\(\left(\beta + 1\right) \left(Z_{E} + r_e\right)\) 
\(r_e + \dfrac{Z_B}{\left(\beta + 1\right)}\) 
\(\dfrac{\alpha\, Z_E}{r_e + \alpha\, Z_E}\) 
B 
C 
CE commonemitter 
\(\left(\beta + 1\right) \left(Z_E + r_e\right)\) 
\(r_o + (1 + A_0) \left(Z_E \parallel r_\pi\right)\) 
\(\dfrac{\alpha\, Z_C}{Z_E + r_e}\) 
E 
C 
CB commonbase 
\(r_e + \dfrac{Z_B}{\left(\beta + 1\right)}\) 
\(r_o + (1 + A_0) \left(Z_E \parallel r_\pi\right)\) 
\(g_m Z_C\) 
E 
B 
(not useful) 



C 
B 
(not useful) 



C 
E 
(not useful) 



In order to properly use the above tables, be careful about the definitions.
For example, the input resistance of a complete common emitter amplifier, including the bias network is: \(R_{in} = Z_B \parallel Z_{in}.\) Similarly, the output resistance of the complete block would be: \(R_{out} = Z_C \parallel Z_{out}.\)
4.2. Smallsignal models
Figure 8, “Hybrid pi model” presents the popular hybridpi smallsignal model of a bipolar transistor for low frequencies.
Figure 9, “T model” is an alternate smallsignal model. Be careful of the base current in this model and properly do KCL! Both models will give exactly the same answer — it makes no real difference which one you choose. However, it does sometimes help the analysis / algebra to choose one over the other, depending on the amplifier type. We will use the hybrid pi model most of the time.
4.3. Single transistor amplifiers
4.3.4. Current source
Labeled in AoE Figure 2.40, p.91 as another one of the basic transistor circuits. Mentioned here for completeness, but this is the amplifier chapter.
4.3.5. Switch
The last of the basic transistor circuits in [AoE].
5. Operational amplifiers
5.1. Cascaded amplifiers
Dave Jones of EEVblog does a good job of walking through the design decisions for his uCurrent GOLD low current measurement tool: EEVblog #572  Cascading Opamps For Increased Bandwidth
6. Tools
This section holds a collection of links to tools hosted here and elsewhere which are useful for work in electronics.
 The ECE department has the following passive parts


All E12 resistor values from 1 Ω to 10 MΩ with 5% tolerance.

All E6 capacitor values from 100 pF to 100 μF in overlapping types.

E3 capacitor values from 10 pF—100 μF and 100 μF—1000 μF.

7. Course Logistics
7.1. Homework assignments
7.1.1. hw01
7.1.2. hw02
7.1.3. hw03
7.1.4. hw04
7.1.5. hw05
7.1.6. hw06
7.1.7. hw07
7.1.8. hw08
7.1.9. hw09
7.1.10. hw10
7.1.11. hw11
7.2. Labs
7.2.1. Lab 1
These are summarized by the work of hw02.
7.2.2. Lab 2
These are summarized by the work of hw04.
7.2.4. Lab 4
The work of hw07 does the hand calculations for these circuits.
7.2.6. Lab 6
The work of hw10 does the hand calculations for these circuits.
7.3. Spring 2018
7.3.1. Week 01
7.3.1.1. Wed  day01  20180110 first day
Introduction to the course and the overall goals, syllabus, book, etc.
7.3.1.2. Fri  day02  20180112
Meet in GEM 166.
Lab activity: predict DC solution, build + measure to compare
hw01 assigned, due Wed Jan 17
7.3.2. Week 02
7.3.2.3. Thu  Lab 1  20180118
Morning section: Lab 1A Emitter Follower
Afternoon section: Lab 1B Current Mirror
7.3.3. Week 03
7.3.3.1. Mon  day04  20180122
Pair up 2on2 to give a 20min tutorial about your lab circuit and learn about the other section’s.
hw02 assigned, due Wed Jan 24.
7.3.4. Week 04
7.3.4.1. Mon  day07  20180129
Review of notation for bias and signal quantities.
Derive gain of a CE amplifier from estimates. The limit as R_{E} → 0 is nonsense, so work on a better model. Begin with the transistor equations and approximation of the EbersMoll equations in active mode. End with an gateway to the concept of trans conductance.
7.3.4.2. Tue  Lab 2 alternate  20180130
Make the measurements of Section 7.2.2, “Lab 2”, get help, etc.
7.3.4.3. Wed  day08  20180131
Taylor series and the smallsignal approximation. Transistor transconductance and smallsignal parameters. Hybridpi model and T model.
References

[[[341notes]]] D. White, ECE 341 Class notes 2018 folder, https://drive.google.com/folderview?id=1hUN1Xicpr9tpCsL2937jfNaCxgpyLT3L

[[[341docs]]] D. White, ECE 341 reference documents folder, https://drive.google.com/folderview?id=0B5O5cSaA0tEQYVpaSnJxMGFrdHM

[AoE] P. Horowitz and W. Hill, The Art of Electronics, 3rd ed. Cambridge University Press, 2015. https://artofelectronics.net

[LAoE] T. Hayes, Learning the Art of Electronics: A HandsOn Lab Course, Cambridge University Press, 2016. https://learningtheartofelectronics.com

[LEC] Tony R. Kuphaldt, Lessons in Electric Circuits, Source version: https://www.ibiblio.org/kuphaldt/electricCircuits/, All About Circuits version: https://www.allaboutcircuits.com/textbook/

[CLbook] Michael F. Robbins, CircuitLab, Ultimate Electronics: Practical Circuit Design and Analysis, https://www.circuitlab.com/textbook/

[TCA] Alfred D. Gronner, Transistor Circuit Analysis, Simon & Schuster, 1970, https://archive.org/details/TransistorCircuitAnalysis

[CMOS VLSI] Neil Weste and David Harris, CMOS VLSI Design  A Circuit and Systems Perspective, 4th edition. AddisonWesley, 2011. http://pages.hmc.edu/harris/cmosvlsi/4e/index.html

[Guidebook] D. White, Guidebook for Electronics II. https://agnd.net/valpo/341/guidebook

[GummelPoon] H.K. Gummel, H.C. Poon, An Integral Charge Control Model of Bipolar Transistors. Bell System Technical Journal, 49: 5. MayJune 1970 pp 827852. https://archive.org/details/bstj495827

[ROHM] ROHM Semiconductor, Electronics Basics, http://www.rohm.com/web/global/en_index

[vishayeseries] Vishay, Standard Series Values in a Decade for Resistances and Capacitances, https://www.vishay.com/docs/28372/eseries.pdf
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