Bipolar transistor operation

Bipolar transistors are named as such because both electrons and holes participate in the device’s operation.

1. List of Tables

Table 1, “Transistor parameter definitions”
Table 2, “Bipolar transistor modes”

2. pn junction diode review

\[v_C(t) = \left( V_{\mathrm{final}} - V_{\mathrm{initial}} \right) \left[1 - \exp\left(\frac{-t}{\tau}\right)\right] + V_{\mathrm{initial}}\]

A little algebra yields an alternate equation:

\[v_C(t) = V_{\mathrm{final}} + (V_{\mathrm{initial}} - V_{\mathrm{final}})\exp\left(\dfrac{-t}{RC}\right)\]

Figure 1. The Gandalf Diode ensures that you never forget which way current flows in a diode.

3. Structure and Physics

Figure Figure 2, “Cross section of a planar BJT” shows the side view of an npn BJT as it would be fabricated on a chip. The order of the three-layer sandwich determines the type (npn or pnp), while the doping level of the outer layers determines the Collector and Emitter terminal labels.

Figure 2. Cross section of a planar BJT

Figure 3. Bipolar current flow in active mode

Where can I read more?

The Wikipedia page Bipolar junction transistor
Lessons In Electric Circuits: Volume III - Semiconductors. Note that this is the exact same content that was later made available at the All About Circuits website.

4. Circuit Models

4.1. Ebers-Moll model

The Ebers-Moll model is accurate, useful, and therefore well-known. It accounts for normal pn junction current flow and the “transistor action” current flow due to the shared middle region.

Figure 4. Ebers-Moll model for NPN

The diode currents for Figure 4, “Ebers-Moll model for NPN” are found in the normal way by their voltages:

\[\begin{align} I_{ED} &= I_{SE} \left[ \exp\left(\dfrac{v_{BE}}{V_T}\right) - 1 \right] \\ I_{CD} &= I_{SC} \left[ \exp\left(\dfrac{v_{BC}}{V_T}\right) - 1 \right] \end{align}\]

Or, using KCL to find the terminal currents:

\[\begin{align} I_E &= & &I_{ED} & - \alpha_R &I_{CD} \\ I_C &= & \alpha_F &I_{ED} & - &I_{CD} \\ I_B &= & (1-\alpha_F) &I_{ED} & + (1-\alpha_R) &I_{CD} \end{align}\]

If we make the substitution \(I_S = \alpha_F I_{SE} = \alpha_R I_{SC}\), the equations become:

\[\begin{align} I_{E} &= & \dfrac{I_S}{\alpha_F} &\left[ \exp\left(\dfrac{v_{BE}}{V_T}\right) - 1 \right] & - I_S &\left[ \exp\left(\dfrac{v_{BC}}{V_T}\right) - 1 \right] \\ I_{C} &= & I_S &\left[ \exp\left(\dfrac{v_{BE}}{V_T}\right) - 1 \right] & - \dfrac{I_S}{\alpha_R} &\left[ \exp\left(\dfrac{v_{BC}}{V_T}\right) - 1 \right] \end{align}\]

Summary to this point: we have a circuit model and set of equations describing the terminal currents given the terminal voltages for a bipolar transistor. There is no notion of operating mode here; this is one set of equations and the rest is plug-and-chug.

Take a minute to also see that the above equations apply equally well to the PNP in Figure 5, “Ebers-Moll model for PNP”.

Figure 5. Ebers-Moll model for PNP

4.2. Gummel-Poon model

The [Gummel-Poon] transistor model is an extension of the Ebers-Moll model to better match measurements and other effects. An important aspect is that it accounts for variation in \(\beta_{F,R}\) as device current changes. It is the default bipolar transistor model used in SPICE. A listing and brief description of the model’s parameters is at the Wikipedia page Gummel-Poon model.

4.3. E-M approximations

Now we will start making some approximations to arrive at some simpler equations. The first is to drop the \(-1\)’s. Doing this only introduces a significant error when the voltages are within a few multiples of \(V_T\), or less than about 100 mV at room temperature.

\[\begin{align} I_{E} &= & \dfrac{I_S}{\alpha_F} &\,\exp\left(\dfrac{v_{BE}}{V_T}\right) & - I_S & \,\exp\left(\dfrac{v_{BC}}{V_T}\right) \\ I_{C} &= & I_S & \,\exp\left(\dfrac{v_{BE}}{V_T}\right) & - \dfrac{I_S}{\alpha_R} & \,\exp\left(\dfrac{v_{BC}}{V_T}\right) \\ I_{B} &= & \dfrac{I_S}{\beta_F} &\,\exp\left(\dfrac{v_{BE}}{V_T}\right) & - \dfrac{I_S}{\beta_R} & \,\exp\left(\dfrac{v_{BC}}{V_T}\right) \\ \end{align}\]

Now, make a few assumptions for the case of an NPN:

The collector is at an equal or higher potential than its emitter, \(v_C \ge v_E\).
The base is also at an equal or higher potential than the emitter, \(v_B \ge v_E\).

4.3.1. Cutoff

Imagine that the base-emitter voltage is near zero (a situation when we can’t ignore the \(-1\), remember). The first \(v_{BE}\) exponential terms will be also near zero. The second \(v_{BC}\) exponential terms will also be near zero or negative. Therefore causing all of the currents to go to zero.

→ This is cutoff mode.

4.3.2. Active

Next imagine that the base-emitter voltage is increased until some reasonable amount of current flows through the forward biased base-emitter pn junction — \(v_{BE}\) will be around 0.6 V. At the same time, the collector voltage is higher than the base, reverse biasing the base-collector junction. The second exponential terms with \(v_{BC}\) will be nearly zero under these conditions and can be ignored.

→ This is forward active mode.

Notice how the collector current is not influenced by the collector voltage.

\[\begin{align} I_E &= \frac{I_C}{\alpha_F} \\ I_C &= I_S \exp\left(\dfrac{v_{BE}}{V_T}\right) \\ I_B &= \frac{I_C}{\beta_F} \end{align}\]

4.3.3. Saturation

Finally, keep the base-emitter junction forward biased but keep increasing the current flowing into the base terminal by increasing \(v_{BE}\). The collector current will necessarily increase and, in a circuit, the effect will be that the collector’s voltage will decrease. Use Figure 6, “Bipolar transistor internal currents” to consider this situation. The labels will be used in the following discussion to refer to specific current components inside the transistor.

Figure 6. Bipolar transistor internal currents

When the collector voltage is greater than the base voltage (forward active), diode Dbc is reverse-biased and therefore Iy is small enough to ignore. This makes Ib = Ix and Ic = Iz, a condition which holds until the base and collector voltages are equal.

( slow down reading here )

Now increase the base voltage so Iz increases. Remember the earlier relationship between base and collector currents: \(i_B = i_C / \beta_F\). This means that Ix and Iz are not independent and Ix = Iz / β_F as well.

Iz is increasing, which is lowering the collector voltage. This causes diode Dbc to become forward biased and start conducting (a little) current. Iy works out to be \(\frac{I_S}{\beta_R} \,\exp\left(\frac{v_{BC}}{V_T}\right)\). The collector voltage will end up at a voltage that satisfies KCL at the collector node to make Ic = Iz - Iy. On the base side, you can see that Ib = Ix + Iy.

Is there any combination of \(\beta_F\) and \(\beta_R\) that allows the collector voltage to drop below the emitter voltage?

The forward biased base-collector junction’s current simultaneously increases the base current and decreases the collector current from their expected values. Since the active mode simplification gives \(\beta_F = i_C / i_B\), we make a new version of β for saturation mode:

\[\beta_{\text{sat}} = i_C / i_B\]

For a recap of saturation mode using this new \(\beta_{\text{sat}}\), remember that increasing \(i_B\) does not increase the collector terminal current Ic (it only increases both Iz and Iy).

You can see this effect by looking at Figure 16 on page 6 of ON Semiconductor’s datasheet for the 2N3904:

Each curve is for a constant collector current (set by an external constant current source).
During the vertical part of each curve, the transistor is in active mode. For example: on the 10 mA curve at \(v_{CE} = 1.0\,\mathrm{V}\), the base current is about \(80\,\mathrm{\mu A}\) making \(\beta_F \approx 125\) in that condition.
As base current increases, the collector voltage does not drop much and approaches 0.1 V.
Take Figure 16 and rotate it 90 degrees counter-clockwise so the plot shows I vs. V.
1. Recall that the base voltage will only increase by 60 mV when the current increases by 10× → in other words consider the base voltage constant.
2. The voltage axis then basically plots the voltage across diode Dbc and its current. Do you see how the collector voltage drops a little to balance KCL at the collector node?

Table 1. Transistor parameter definitions
Term	Name	Definition
\(\beta\)	common-emitter current gain	\(\beta = \dfrac{i_C}{i_B}\)
\(\alpha\)	common-base current gain	\(\alpha = \dfrac{i_C}{i_E}\)
	relationships	\(\beta = \dfrac{\alpha}{1 - \alpha}\\ \alpha = \dfrac{\beta}{\beta + 1}\)
\(V_T\)	thermal voltage	\(\dfrac{k_B T}{q} \approx 26\,\mathrm{mV} \text{ at } 300\,\mathrm{K} \text{(room temp)}\)
\(V_A\)	Early voltage	≈ 100V for discrete or 20V on IC
\(\beta\)	for hand analysis	≈ 100 for discrete or 20 on IC

[AoE] only just mentions Early voltage and refers you to “Chapter 2x” of a (future) supplemental book. See Wikipedia: Early effect for a good description of this phenomenon.

Table 2. Bipolar transistor modes
B-E junction	B-C junction	Mode	Behavior (npn, swap E↔B and E↔C for pnp)
Reverse	Reverse	cutoff	\( \begin{cases} i_C \approx 0 \\ i_B \approx 0 \\ V_{BE} \ll 0.6 V \end{cases} \)
Forward	Reverse	active	\( \begin{cases} V_{BE} \approx 0.6 V \\ V_{CE} \rightarrow \text{set by circuit conditions and } > V_{CEsat} \\ i_C = \begin{cases} \alpha \, i_E \text{, or } \approx i_E\\ \beta \, i_B \\ I_S \exp \left( v_{BE} / V_T \right) \end{cases} \\ i_B = i_C / \beta \text{, or } \approx 0\\ \end{cases} \) Figure 7, “npn hand model - no base current” and next
Forward	Forward	saturation	\( \begin{cases} V_{BE} \approx 0.6 V \\ V_{CE} = V_{CE sat} \approx 0.1 V \\ i_C \rightarrow \text{set by circuit conditions and } > 0 \\ i_B \rightarrow \text{must be } > I_C/\beta > 0 \\ (i_E > i_C \text{ by KCL}) \end{cases} \) Figure 11, “npn hand-calculation saturation model” and next
Reverse	Forward	rev-active	(your transistor is in backwards)

4.4. Hand-calculation models

There is a section at the end of most chapters in [CMOS VLSI] called “Pitfalls and Fallacies” which gives some hints on where it is easy to over- or under-think an issue. A favorite that applies to this context is:

Using excessively complicated models for manual calculations:

Because models cannot be perfectly accurate, there is little value in using excessively complicated models, particularly for hand calculations. Simpler models give more insight on key trade-offs and more rapid feedback during design.

— [cmosvlsi] section 2.6, page 93

The most important task is to figure out (a.k.a. guess-then-check) which mode the transistor is operating in. Remember that it is the states of the two pn junctions which determine the mode. See the table Table 2, “Bipolar transistor modes” for a summary of these modes and the equations that are useful.

4.4.1. (forward) Active mode

Ignoring base current (Β → ∞, α → 0, or i_B → ∞):

Figure 7. npn hand model - no base current

Figure 8. pnp hand model - no base current

Including base current:

Figure 9. npn hand-calculation model - including base current

Figure 10. pnp hand-calculation model - including base current

4.4.2. Saturation

Figure 11. npn hand-calculation saturation model

Figure 12. pnp hand-calculation saturation model

4.4.3. Example 1 analysis

Figure 13. Example circuit with both collector and emitter resistors

Use the following values with Figure 13, “Example circuit with both collector and emitter resistors”:

VB = 2.0 V
Vcc = 5.0 V
Rc = 1 kΩ
Re = 1 kΩ

Steps to quickly find the DC solution of this circuit:

Guess a mode → active.
Vb is known, so find Ve as 2.0 - 0.6 = 1.4 V.
The voltage across Re is now know, so find Ie as 1.4 V / 1 kΩ = 1.4 mA.
β is large (and \(\alpha_F \approx 1\)), so just estimate Ic = Ie. This is the model of Figure 7, “npn hand model - no base current”.
This is enough to find the (node) voltage at the collector as (5 V - 1.4 mA × 1 kΩ) = (5 - 1.4) = 3.6 V.
That’s it! … wait, not until we check the mode:
1. Vc > Vb so Q1 is indeed in active mode.
2. Done.

Open up CircuitLab schematic ce-re-example and run a DC Simulation. Click on the nodes and device terminals to see the various node voltages and currents.

Notice that the simulator (which is SPICE underneath) reports the emitter current as negative. It turns out that SPICE defines all device currents as positive into the terminals. Also notice that the current changes sign when probing the current at either end of a resistor. Here also, SPICE uses polarized resistors, which is basically the + and - terminals are defined graphically before simulation.

4.4.4. Example 2

Keep the same conditions as above, except change:

Rc ⇒ 10 kΩ

Not much changes on the emitter side of the circuit, so no need to re-do the math.

Find Vc as (5 V - 1.4 mA × 10 kΩ) = (5 - 14.0) = -9.0 V.
The first clue is a negative node voltage when there are no negative supply voltages.
The second is to check the operation mode:
1. Vb > Ve so the B-E junction is forward biased. (no surprise since we forced this)
2. Vc < Vb so the B-C junction is also forward biased. This violates our starting assumption of active mode. The solution is to re-do the problem but assume a different mode (saturation).

Take another swig of coffee and start over. Oh wait, saturation only changes the collector side. All of the emitter side math stays the same.

Set Vce to 0.1 V according to the table.
Therefore Vc is 1.5 V.
Ic calculates to (5.0 - 1.5) / 10 kΩ = 0.35 mA.
If it is useful, we can use KCL to compute the base current as Ie - Ic = 1.05 mA.
The check is to see if base current is larger than what is predicted by \(\beta_F\). It is obviously larger than Ic / β, so the check passes.

Check that these numbers are close to what is simulated (which uses the Section 4.2, “Gummel-Poon model”) in the same CircuitLab schematic as the first example.

Finally, compute \(\beta_{\text{sat}} = 0.35 / 1.40 = 0.25\). This number is useful to see how deep into saturation the transistor is. Here, it is approximately ocean-floor-deep saturation mode.

4.5. Rules of thumb

4.5.1. Ratio rules

Assuming two transistors are matched (their parameters such as I_S and temperature are exactly the same):

\(\dfrac{I_{C2}}{I_{C1}} = \exp\left(\dfrac{\Delta V_{BE}}{V_T}\right)\)
\(\Delta V_{BE} = V_T \ln\left( \dfrac{I_{C2}}{I_{C1}} \right)\)

4.5.2. Temperature dependence

[positive emphatic slang here], this is an important topic! IMNSHO, properly dealing with temperature dependence over the entire range of intended operational temperatures separates the professional from the amateur circuit designer.

When talking about your designs:

It just works … always.

— Anyone (except you of course)

It may seem from Section 4.5.1, “Ratio rules” that temperature only shows up as \(V_T = \frac{k_B\,T}{q}\). Remember that the saturation current I_S is also a strong function of temperature (T⁴ !). The following relationships work well over nearly the entire electronics temperature ranges (very cold is interesting to Physicists, and much hotter and things start melting):

Constant I_C

\(\Delta V_{BE} \approx -2.1 \,\mathrm{mV / ^\circ C}\)
\(\propto 1 / T\,\mathrm{(K)}\)

Constant V_BE

\(\Delta I_C \approx 9\,\mathrm{\% / ^\circ C}\)
\(2\!\times I_C \text{ for } \Delta T = 8\,\mathrm{^\circ C}\)

References

[[[341-notes]]] D. White, ECE 341 Class notes 2019 folder, https://drive.google.com/drive/folders/1vzdLxzTUAC6xXF6YjVcDRuy_BKR7gzDz?usp=sharing
[[[341-docs]]] D. White, ECE 341 reference documents folder, https://drive.google.com/folderview?id=0B5O5cSaA0tEQYVpaSnJxMGFrdHM
[AoE] P. Horowitz and W. Hill, The Art of Electronics 3rd ed. (affiliate link), Cambridge University Press, 2015. https://artofelectronics.net
[L-AoE] T. Hayes, Learning the Art of Electronics: A Hands-On Lab Course (affiliate link), Cambridge University Press, 2016. https://learningtheartofelectronics.com
[LEC] Tony R. Kuphaldt, Lessons in Electric Circuits, Source version: https://www.ibiblio.org/kuphaldt/electricCircuits/, All About Circuits version: https://www.allaboutcircuits.com/textbook/
[CL-book] Michael F. Robbins, CircuitLab, Ultimate Electronics: Practical Circuit Design and Analysis, https://www.circuitlab.com/textbook/
[TCA] Alfred D. Gronner, Transistor Circuit Analysis, Simon & Schuster, 1970, https://archive.org/details/TransistorCircuitAnalysis
[CMOS VLSI] Neil Weste and David Harris, CMOS VLSI Design - A Circuit and Systems Perspective, 4th edition. Addison-Wesley, 2011. http://pages.hmc.edu/harris/cmosvlsi/4e/index.html
[Guidebook] D. White, Guidebook for Electronics II. https://agnd.net/valpo/341/guidebook
[Gummel-Poon] H.K. Gummel, H.C. Poon, An Integral Charge Control Model of Bipolar Transistors. Bell System Technical Journal, 49: 5. May-June 1970 pp 827-852. https://archive.org/details/bstj49-5-827
[ROHM] ROHM Semiconductor, Electronics Basics, http://www.rohm.com/web/global/en_index
[vishay-e-series] Vishay, Standard Series Values in a Decade for Resistances and Capacitances, https://www.vishay.com/docs/28372/e-series.pdf