Figure 1. Schematic of a phase-splitter

## 1. Lab goals

Topics
• Transistor operation modes: active, saturation, cutoff. Identifying these modes by observation of waveforms.

• Quickly building and measuring small transistor circuits with no wiring errors.

Each of the two lab sections are doing different activities.

Your task is to learn about the concepts using Figure 1, “Schematic of a phase-splitter” as your example and describe your findings to your classmates who did the other activity. The focus topics are similar between the two sections, however. This allows everyone several angles by which to learn the concepts. A secondary goal is to increase your technical communication / teaching skills through action.

## 2. Activities

Begin with only the circut of Figure 1, “Schematic of a phase-splitter” contained inside the Step 1 box.

Set `Rc` to zero for this lab.

### 2.1. DC conditions

Select values of `R1` and `R2` to make the emitter voltage near 0 V.

• What is the condition required at the base node? (node voltage)

In order to make this selection to be less sensitive to transistor properties, we want the current through `R1` and `R2` to be 10× to 20× larger than the transistor’s base current. This allows us to ignore base current for quickly estimating the base node voltage while also yielding a real bias condition that is close to the predicted value.

10× to 20× this base current is then your target current through `R1`.

• Find a `R1` value that meets this condition and is in stock.[1]

• Calculate the required `R2` value and round to a value that is in stock.[1]

→ Alternate way to find `R1` and `R2`: view as a voltage divider and use the Best Voltage divider resistor calculator ever - agnd.net

Build this circuit and verify that the emitter voltage is indeed near 0 V.

### 2.2. Amplifier

Now setup the circuit contained in the Step 2 box. Use the bench-top function generator or AD2 function generator output `W1` as source Vs

Use oscilloscope channel 1 to view the node voltage at B (between B and zero) and channel 2 to view out.

Set an initial amplitude of 200 mV peak-to-peak.

Verify that the amplifier is working as a voltage follower.

Now, increase the input signal amplitude until the output voltage starts to have some “issues”. Set the amplitude to 6 V peak-to-peak.

• Your task is to figure out why the output looks the way it does!

• Then you should make a short document describing what you did and your explanation of the last waveforms.

Circuit notes

The amplifier’s output voltage will track the input voltage with about a 0.7 V downward shift (VBE). However, at large amplitudes, the output will clip at about -1.5 V.

As the input (base) voltage and therefore output / emitter voltage decreases, the emitter current decreases. This current is easily found by fixing VE and solving for the currents at the emitter node via KCL. Emitter current eventually reaches zero and will not become negative because the transistor is now in cutoff mode. The equivalent circuit at node out in this condition is merely a voltage divider between -5 V and zero involving `Re` and `Rload`.

Section 2.2.3.D of [AoE] also discusses this behavior of a resistively-biased EF. In addition, [L-AoE] sections 4N.4.4 and 4N.4.5 add some nice explanation and points out the power dissipation problem that rears its head as soon as you try to get more voltage swing by lowering `Re`.

## References

1. The GEM 163 storage cabinet has every E12 series value from 1 Ω to 10 MΩ