1. Review formulas

1-pole RC high-pass filter:

\[H(f) = \dfrac{j\dfrac{f}{f_H}}{1 + j\dfrac{f}{f_H}} \quad\text{with}\quad f_H = \dfrac{1}{2\pi R C}\]

1-pole RC low-pass filter:

\[H(f) = \dfrac{1}{1 + j\dfrac{f}{f_H}} \quad\text{with}\quad f_H = \dfrac{1}{2\pi R C}\]

If you make the following assumptions:

  • The open-loop gain Av0 is large enough, which means \(\gg \left(1 + \frac{R_f}{R_1}\right)\)

  • The opamp’s open-loop output impedance Zout is low enough, or much less than the impedance seen by the output node (for this lab = 50,047 Ω).

The total non-inverting opamp output from the input signal and DC errors VOS and (IB, IOS) ←→ (IB+, IB-) is:

\[v_{OUT} = v_{in}\underbrace{\left(1 + \dfrac{R_f}{R_1}\right)}_\text{gain} + \underbrace{\biggl(V_{OS} + I_{B+} R_{eq+} - I_{B-} R_{eq-}\biggr)\left(1 + \dfrac{R_f}{R_1}\right)}_\text{offset}\]
  • \(R_{eq+}\) and \(R_{eq-}\) are the impedances seen by the + and - input terminals of the opamp.

Figure 1. Discrete opamp schematic
opamp lab6
Figure 2. Variable gain non-inverting amplifier

2. Procedure

Construct your Lab 5 opamp of Discrete opamp schematic. Then use this as a normal “triangle” opamp and construct the circuit of Variable gain non-inverting amplifier. Instrument this circuit with your AD2 with the connections shown.

Open WaveForms and startup the Wavegen and Scope panels.

Setup the system so the amplifier output is a 1 Vp-p, 1 kHz sinusoid centered around 0 V and is operating at a gain of 100 V/V (adjust the potentiometer).

Make note of the W1 input amplitude.

Verify that the amplifier is operating correctly with a clean output waveform centered near 0 V.

Open the Network panel in WaveForms and set it up with the following parameters:

  • Upper row settings

    • Scale: Logarithmic

    • Start: 100 Hz

    • Stop: 10 MHz

    • Samples: 100

  • Right side settings

    • WaveGen: set to the same offset and amplitude as the current WaveGen values

    • Magnitude

      • Units: dB

      • Top: 70 dB

      • Bottom: 0 dB

    • Phase

      • Offset: -90°

      • Range: 180°

☆ This setup plots the magnitude and phase of your amplifier’s transfer function!

Verify that the low frequency gain is still 100 V/V, remember the conversions between dB and linear voltage units:

  • \(\text{gain (dB)} = 10 \log_{10} \Big\lbrack(\text{V/V})^2\Big\rbrack\)

  • \(\text{gain (V/V)} = \sqrt{10^{\text{(dB)}/10}}\)

or, simplified to the perhaps more familiar form:

  • \(\text{gain (dB)} = 20 \log_{10} \Big\lbrack\text{(V/V)}\Big\rbrack\)

  • \(\text{gain (V/V)} = 10^{\text{dB}/20}\)

The frequency response plot is only valid when the system is linear, meaning the input and output signals are all within proper ranges to not clip or otherwise be distorted. One nice way to check this is to turn on the oscilloscope view at the same time. Do this by selecting menu item View ▸ Time.

Vary the potentiometer to set your amplifier to several low-frequency gains and measure your amplifier’s -3 dB frequency. Also compute the gain-bandwidth product at each setting (GBW is computed with gain in linear units, not dB).

Gain (dB) fH (-3 dB) GBW (MHz)








Notice the following characteristics of these measurements
  • When low-frequency gain increases, the bandwidth decreases by the same proportion.

  • GBW is relatively constant.

  • GBW is nearly the same as the unity gain (1 V/V, 0 dB) frequency, fT.

  • The phase is -45° at the -3 dB frequency, exactly as predicted by the transfer function math.

3. Old Lab 5 notes for reference

Construct the opamp of Discrete opamp schematic on a small section of breadboard. The capacitor Cc helps to stabilize this amplifier, but you can greatly help the situation by minimizing the length of jumper wires in the construction.

  • Be sure to allow yourself easy access for replacing capacitor Cc and for attaching meters to nodes ina, inb, and out.

  • Use the physically small ceramic capacitor types for Cc.

  • Add a large capacitor (1 to 10 μF) between the Vcc and Vee nodes to help reduce the effect of the long wires connecting to the power supply.

  • For each of the 3 npn transistors: use the “diode check” mode on the multimeters to measure VBE. Select the transistors with the closest values as Q1 and Q2. Since VBE is sensitive to temperature changes, it is best to minimize touching the transistors until you’ve measured them (use pliers).

  • Do a similar procedure to select your Q3 and Q4 pair.

Figure 3. Compact construction example

See Compact construction example for an example of pre-bending transistor leads and building the circuit in the same general arrangement as the schematic. This makes troubleshooting easier since the geometry is similar and reduces the parasitic inductances and the electric and magnetic coupling between nodes and loops.

Figure 4. Vertical

Several of the resistors are bent to be in a vertical position. Bend and trim your resistor leads as shown in Vertical
. The right lead in the figure makes for a convenient loop for attaching probes.

4. References