Diode logic gates

Name:

1. Procedure

guess (fwd / rev bias) state of each diode
redraw circuit, replacing diode with its model
solve for V_Dx or I_Dx for each diode
check corresponding condition
(repeat) until all checks pass
Solve for other circuit quantities as needed

2. Gate 1

diode or v

Table 1. Logic function:
V_A	V_B	V_Y
0	0
0	5
5	0
5	5

2.1. Inputs: A=0 V, B=0 V

2.2. Inputs: A=0 V, B=5 V

3. Gate 2

diode and v

Table 2. Logic function:
V_A	V_B	V_Y
0	0
0	5
5	0
5	5

4. Gate 3

diode and or

Table 3. Logic function:
V_A	V_B	V_C	V_x	V_y	V_out
0	0	0
0	0	5
0	5	0
0	5	5
5	0	0
5	0	5
5	5	0
5	5	5