This lab constructs and measures the static and dynamic performance of a CMOS inverter.

The additional purpose is to observe and correlate physical construction details with measured performance characteristics. By the end of this lab you will better understand that almost all aspects (large and small) of the waveforms you measure and see on an oscilloscope have a definite cause and can be related to the circuit and measurement setup. The only randomness in the circuit is the small amount of “fuzz” on the waveforms due to thermal noise or the influence of external electric and magnetic fields.

1. Introduction

Careful observation of a circuit’s response to various inputs can reveal many characteristics. This is similar in concept to the fact that knowing the impulse response of a linear system tells you everything about that system.

Rise times can be used to estimate the effective capacitance at a node, waveform slopes can be used to measure or estimate transistor currents without resorting to ammeters or adding current-measuring resistors to the circuit.

Parasitic inductance and capacitance as a result of physical construction can greatly affect circuits with very fast edges, short delays, or high frequencies. The mere act of attempting to measure a circuit changes its characteristics. Good measurement and construction techniques can minimize these disturbances, but not entirely eliminate them.

1.1. Capacitors

This is the time to also recall everything you know about how capacitors behave.

Current through a capacitor:

\[i_C(t) = C \dfrac{\mathrm{d} }{\mathrm{d} \, t}\left[v_C(t)\right]\]
(dis)charge via a resistor

Charging or discharging capacitors through a resistor gives waveforms of the shape:

\[v_C(t) = V_F + (V_I - V_F)\exp\left(\dfrac{-t}{RC}\right),\]

where \(\tau = RC\) in units of seconds, and where \(V_I \triangleq v_C(t=0)\) and \(V_F \triangleq v_C(t\rightarrow \infty)\). In other words, shift the time reference so the transient response begins at \(t=0\).

(dis)charge via a constant current

Charging or discharging a capacitor with a constant current gives waveforms with linear slopes (triangles!).

\[\begin{align} I_{\mathrm{constant}} &= C \dfrac{\mathrm{d} }{\mathrm{d} \, t}\left[v_C(t)\right] \\ \nonumber \\ \dfrac{\mathrm{d}\,v_C}{\mathrm{d}\,t} &= \frac{I_{\mathrm{constant}}}{C} \end{align}\]

If the current is going out of the capacitor (negative), the voltage is decreasing (also negative).

Today, you will see very little R-C type behavior from your circuit. Most of the behavior is from MOSFET saturation mode (constant currents) and L-C damped ringing from the parasitic inductance of your wiring.

1.2. MOSFETs

N-channel triode mode drain current
\[i_D\mathrm{(triode)} = \mu_n C_{ox} \frac{W}{L} \left[ \left(v_{GS} - V_{TN}\right) v_{DS} - \frac{v_{DS}^2}{2} \right] \label{triode}\]

The channel thickness on the drain side of the FET goes to zero (or starts from zero) when vGD is equal to the threshold voltage, it is algabraically the same (with KVL) to also say:

\[\begin{align} v_{GD} &= V_{TN} \\ & \mathrm{substitute\;}v_{GD} = v_{GS} - v_{DS} \\ v_{GS} - v_{DS} &= V_{TN} \\ v_{DS} &= v_{GS} - V_{TN} \label{vdssat} \end{align}\]

At the boundary between triode mode and saturation mode, substitute equation \(\eqref{vdssat}\) into equation \(\eqref{triode}\) to get

N-channel saturation mode drain current
\[\begin{align} i_D\mathrm{(sat)} &= \mu_n C_{ox} \frac{W}{L} \left[ \left(v_{GS} - V_{TN}\right) \left(v_{GS} - V_{TN}\right) - \frac{\left(v_{GS} - V_{TN}\right)^2}{2} \right] \\ \star\quad i_D\mathrm{(sat)} &= \frac{\mu_n C_{ox}}{2} \frac{W}{L} \left(v_{GS} - V_{TN}\right)^2 . \label{sat} \end{align}\]

  • In saturation mode, the drain current is constant.

  • In triode mode, the drain-source behaves like a resistor.

cmos inverter
Figure 1. CMOS inverter
cmos inverter ringing
Figure 2. CMOS inverter with wiring-related parasitics

2. Experiment

Parts needed:

  • BS170 n-channel MOSFET and _ _ _ _ _ p-channel MOSFET

  • _ _ _ _ _ \(\mathrm{\mu F}\) electrolytic capacitor for \(C_S\). “power supply bypass capacitor”

  • _ _ _ _ _ \(\mathrm{nF}\) film or ceramic capacitor (red or yellow) for \(C_{load}\)

  • 2 oscilloscope probes

  • BNC to minigrabber cable

  • Small solderless breadboard

It may be useful to refer to the oscilloscope’s manual. A copy is posted in the Docs folder in Google Drive.

When beginning a session with your oscilloscope, always reset it back to Factory Default settings! Default Setup → Factory Default

2.1. Without capacitors

Construct the circuit shown in Figure 1 except for the capacitors.

Set the function generator frequency to \(200\,\mathrm{kHz}\) with a square wave from \(0\,\mathrm{V}\) to \(5\,\mathrm{V}\), 50% duty cycle.

Setup the four measurement slots on the oscilloscope display to measure the output’s 10% to 90% \(t_{rise}\) and \(t_{fall}\) times, and both propagation delays \(t_{pLH}\) and \(t_{pHL}\).

A \(t_{pHL}\) delay is measured from the 50% point of the input waveform to the 50% point of the output waveform when the output transitions from high to low)

Adjust the triggering setup, the horizontal time scale, and vertical voltage scales to view only one transition at a time. Make the edge of the transition time take up 1/4 or more of the horizontal space. Ensure the display includes the final value of the transition after any ringing, the Measurement functions need this flat portion to properly detect the low and high logic levels.

Record the four measured times.

Change the trigger settings to see the other edge. Don’t waste your time zooming and scrolling.

There is nothing to submit directly from this lab. However, there will be a few Exam 2 questions that presume you did the measurements and observed the effects seen in this activity.

The bullet points below are historical, and also FYI that the 'scope has this capability.

  • [ DOES NOT WORK ] Use the BenchVue PC software to save the oscilloscope’s waveform data of each of the two transitions to .csv files. Open them to verify that the files have 3 columns: time, \(V_{in}\), and \(V_{out}\).

  • Alternate: Use a USB Flash drive in the oscilloscope. Save → select Format → CSV data. Be sure that your screen shows exactly the data you wish to save.

  • Capture the output rising transition into reference waveform R1 using the oscilloscope. Do this from the Ref button on the far right. You will use this to compare waveforms between different circuits.

Carefuly observe and record or sketch the input and output waveform shapes. Note the cause-effect and interaction between the each waveform. Look for L-C ringing shapes after the waveform edges.

Notice how the output doesn’t begin dropping until the input voltage reaches the NMOS threshold voltage, turning the lower transistor ON and pulling down the output voltage.

Notice how after each edge there is substantial ringing on every node you probe. Figure 2 shows all of the L-C circuits that are being "activated" (unit-step functions) at each edge.

Notice how the input voltage remains at approximately the threshold voltage for a short time, exactly the same time that it takes the output to change state. Then the input finishes its transition. With the \(50\,\Omega\) output resistance of the signal generator you can estimate the current that is charging the gate capacitances.

2.2. Rebuild with no capacitors

Rebuild your circuit without using any jumper wires. All of the connections can be made using only 4 breadboard strips (since there are only 4 nodes in the circuit).

Use random resistor lead wires to connect the signal generator, power supply, and oscilloscope probes. This makes changing the circuit easier.

Record the same four measured edge and delay times.

Overlay the output waveform from your original circuit, stored as R1, on top of the current output rising waveform. Notice how the new waveform has much less ringing?

  • Save a screenshot of this display

Nothing changed with the schematic of the circuit, just the physical construction. Figure 2 shows all of the inductors that are introduced into the circuit by all of the long wires. Making all connections short in length directly reduces the value of all those inductors. This is one of many reasons why high-performance, especially high-speed, circuits are physically small.

  • Save your new output rising waveform as R2.

2.3. With \(C_S\) added

Now, connect capacitor \(C_S\) between the two power supply terminals very close to the transistor terminals. Be sure to observe the capacitor’s polarity, electrolytic capacitors only behave properly if their applied voltage is in the correct orientation.

  • Record the (4) new transition time measurements.

  • Save the waveform data to another set of .csv files.

  • Observe and describe the changes that happened to the waveforms. Which aspects changed? Can you explain why or what caused the changes? It will be helpful to alternate between the capacitor in and out of the circuit while watching the display.

  • Save the output rising transition as R1, overwriting the original saved waveform.

2.4. With both \(C_S\) and load capacitor \(C_{load}\) added

The purpose of adding \(C_{load}\) to the output is to purposefully slow down the output transition. This allows us to separate the transistors' ON/OFF transitions from the condition of the output node’s capacitance being charged or discharged by a single transistor.

  • Record the (4) new transition time measurements.

  • Save the waveform data to another set of .csv files.

Make the same observations as the previous section.

Is the output rising edge an exponential shape? What shape(s) make up the rising edge waveform.

  • Probe the \(+5\,\mathrm{V}\) power supply node directly at the Source of the PMOS transistor. Remove and replace the power supply capacitor \(C_S\) while monitoring the \(+5\,\mathrm{V}\) node. Which transition (output rise or fall) affects the situation the most? Why is this so? How good of an assumption is it that the power supply voltage is always and actually constant?

  • Replace the capacitors so both are back in circuit.

  • Estimate the PMOS and NMOS transistor’s maximum drain currents using the (slope of the) output waveform and the fact that you know the capacitance at the output node.

From these currents, also estimate each transistor’s \(K_n = \left(\mu_n C_{ox} \frac{W}{L}\right)\) or \(K_p = \left(\mu_p C_{ox} \frac{W}{L}\right)\) value. (Which mode is the transistor in during the largest output slope?) In this process, you will need to, somehow (e.g. both observations and datasheets), estimate your transistors' \(V_{TP}\) and \(V_{TN}\).

2.5. With only \(C_{load}\)

While monitoring the output’s rising edge, remove the power supply bypass capacitor \(C_s\).

  • Record the new time measurements.

  • Save the waveform data to another set of .csv files.

Switch back and forth between \(C_s\) in and out of the circuit. Observe how the output rising edge shape varies between the waveform shape derived in class (linear slope) and that of a step response of an under-damped L-C circuit. Note how the delay and rise-time changes.

Remove the load capacitor \(C_{load}\), leaving only \(C_s\). Can you re-build your circuit and measurement setup to obtain as clean of waveforms as possible? How much overshoot and ringing can you eliminate by careful construction?

Do not use oscilloscope settings to cleanup the displayed waveform, use the scope to clearly show all details of the waveforms. Use Normal mode for the [ Waveform → Acquire ] mode, not Averaging or High Resolution.

Describe and document what changes or construction techniques you used to obtain these waveforms.

3. Report

There is no formal report attached to this lab activity.

Old info below

However, you should have your own copy of the eight (8) .csv files of waveform data, one for the output rising transition and one for the output falling transition for each of the 4 possible combinations of \(C_{S}\) and \(C_{load}\) present in the circuit. Each file needs to contain time, \(V_{in}\), and \(V_{out}\) columns.

Create a ZIP file of your 8 .csv files. Use the filename: lastname_firstname_lab6.zip and submit to the Blackboard turn-in section.

Each csv file should be named rise_Cs_Cload.csv or fall_Cload.csv (follow the pattern).

The next homework is to use your AD2 to capture the same waveform data with this same circuit and compare the two data sets by plotting.