Q: PC bit width

The PC needs enough bits to address (point to ) every location in program memory. Therefore, you need to know how much program memory there is AND how it’s addressed.

ATtiny85 has 8 KiB of program memory (flash), which is addressed as 16-bit words. So, this is 4 Ki locations, which is 22 × 210 (kibi multiplier), or 12 bits.

ATmega328P has 32 KiBof program memory (flash), also addressed as 16-bit words. So: 32/2 = 25-1, and 4 + 10 = 14 bits to address everything.

The CPU in the MSP430FR6989 can address 1 MiB of memory of 8-bit bytes. The SI prefix mebi (Mi) means 220, so the Program Counter needs to be 20 bits wide.

Q: Why instruction aliases?

Though the branch instructions all have the same form, the meaning of the branch is different for these different status bits.

It is easier to read assembly code that reads “branch if same or higher,” for example, than directly asking about the status bit positions themselves. With an assembler that allows macros, a programmer would define an alias anyway:

.macro brsh
    brbc 0, @0
.endmacro

; ... later ...

    brbc SomeLabel

See AVR-assembler_Microchip.pdf for more information about assembler macros. They are quite similar to C Preprocessor macros (#define name(arg, …​) value), but you are not likely to be familiar with them.

Q: Skip instructions vs. branch?

The “skip next instruction” can be emulate by a branch to a label after the next instruction (PC ← PC + 2).

; clear PB3 only if it is currently set
    sbic PORTB, 3
    cbi  PORTB, 3
    nop             ; continuing on...


; alternate form without SBIS
    in r16, PORTB   ; read the register
    bld r16, 3      ; pin PB3 to T  (handy, isn't it!)
    brtc Continuelll
    cbi PORTB, 3
Continue:
    nop             ; continuing on...

There are two pairs of skip-if instructions because the Register File and the I/O Registers are different hardware.

The Register File Registers and the I/O Registers are in the same Data Memory address space, so it is possible to have a single pair of skip-if instructions. Perhaps there was not room in the instruction opcode encoding to accommodate enough bits to fully encode the (32 + 64) options.

You can also begin to see why only 16 of the 32 Register File Registers support immediate instructions (where the instruction includes a constant).