1. Transistor capacitances

Weste and Harris §2.3, pages 68—​73.

  • Gate capacitance

    • Channel capacitance

    • Gate-Drain overlap

    • Gate-Source overlap

  • Diffusion (pn-junction) capacitances

    • bottom area

    • side wall perimeter

2. BSIM4 MOSFET model

BSIM3 is a physics-based, accurate, scalable, robust and predictive MOSFET SPICE model for circuit simulation and CMOS technology development. It is developed by the BSIM Research Group in the Department of Electrical Engineering and Computer Sciences (EECS) at the University of California, Berkeley. The third iteration of BSIM3, BSIM3 Version 3 (commonly abbreviated as BSIM3v3), was established by SEMATECH as the first industry-wide standard of its kind in December of 1996. BSIM3v3 has since been widely used by most semiconductor and IC design companies world-wide for device modeling and CMOS IC design.

— BSIM Group at UC Berkeley
https://www.bsim.berkeley.edu/models/bsim3

From the 0.5 μm process with λ=0.3 μm: c5.txt:

  • XL = (drawn channel length) - (actual channel length)

  • CJ with MJ

  • CJSW and CJSWG with MJSW and MJSWG

  • CGDO and CGSO

3. Modeling in LTspice

AD, AS, PD, PS

use parameters!

4. Inverter model schematic

transistor capacitances → input and output capacitances