1. LTspice simulation examples

  • PMOS → P error evidence

  • .measure statements and results. SPICE Output Log (Ctrl+L)

inverter start

2. Inverter capacitances

  • Cgs, Cgd, Cgb

  • Cdb, Csb

  • Input capacitance

  • Output (self) capacitance

  • Load capacitance

As function of transistor sizes.











3. Inverter drive strength

Maximum drain current

\[i_D (sat) = \frac{k_n}{2} \frac{W}{L} \left(V_{GS} - V_{TN}\right)^2\]

Effective resistance

\[R_N \approx \frac{V_{DD}}{i_D (sat)}\]

Delay estimate:

  • Total load capacitance

  • Charging current

  • \(\Delta V_{out} = \frac{V_{DD}}{2}\)