Exam 1 is in-class, Monday March 26.

Direct link to 2018-03-24_429-board.pdf, the whiteboard from Friday’s class time.

1. Topics and comments

One of the best ways to review the content that will be on the exam is to go over the homework problems assigned thus far. Solutions to those problems are on Blackboard in the Content section. This cannot be over emphasized: each homework problem was there for a purpose related to the course content and not just busywork!

  • MOSFET device equations, operation modes. vgs, vds, id. Most important is the behavior that the equations predict, such as

    • If X voltage changes, how does drain current change.

    • The effective D-S resistance is affected by Y.

  • MOSFET capacitances.

    • Given process information (like c5.txt and similar) and the geometry of a FET, find the various capacitance values.

  • → For a CMOS inverter, why is the parasitic (no load) delay relatively constant even when increasing the transistor sizes (to lower ON resistance)? ←

  • Describe the reasoning that the channel length of FETs in logic circuits are nearly always as short as possible. In what situations is it useful to increase the channel length?

  • → Logical Effort analysis and design technique. ←

    • Given a schematic of an arbitrary combinational logic gate, find its logical effort, g.

    • electrical effort h and H

    • path effort F, and stage effort f

    • Given several gate-level schematics which implement the same desired logic function, predict which variation will have the lowest dealy. Use Logical Effort in your reasoning. (p4.11)

    • Given a gate-level schematic and a fixed load (capacitance), find each gate’s optimum size to minimize path delay.

    • Estimate the delay of a path using L.E.

  • → Design an inverter chain to drive a large load capacitance. ← (hw08) Determine the “best” design using different metrics:

    • Total transistor (gate) area / chip area required.

    • Shortest delay with a maximum total gate area constraint.

    • Absolute minimum delay.

    • Lowest energy per transition. ← bonus candidate!

  • Software skillz. Electric and LTspice.

    • Given a set of simulation waveforms, find various parameters such as delays or rise/fall times.

    • Find Electric schematic errors or interpret error messages with suggested fixes.

    • Match simulated waveforms to the schematic they come from. (several waveforms + several schematics match-up game)

2. References

Reference Documents G-Drive folder

Class notes G-Drive folder