1. Key concepts

Nodes

Ports where arcs (wires) connect

Arcs

(can) have constraints

Cell - collection of nodes and arcs

  • views - schematic, layout, icon, etc

  • exports define outside connections

Cell instances

  • may be placed in other cells as nodes

  • up/down hierarchy

Library

  • collection of cells

  • single *.jelib file on disk

A complete circuit may span use several libraries — the top-level cell contains entire circuit representation.

2. Tasks

This is an individual assignment.

  • Create a new library named lastname_tutorial, where lastname is your last name in lower-case with no spaces in the file name. This naming format is strictly required![1]

If you are paranoid, re-import the custom preferences electricPrefs-ECE429-v1.xml then restart Electric.

  • Follow the tutorial in the manual section 1-10: IC Layout Tutorial

Save your library!

  • Follow the tutorial in the next manual section 1-11: Schematic Tutorial

Save your library!

  • Follow the tutorial in the next manual section 1-12: Schematics and Layout Tutorial

Save your library!

  • You are welcome, but not required, to simulate your AND gate with IRSIM. It is useful for simulating larger circuits without dealing with the full accuracy of LTspice.

  • Upload your lastname_tutorial.jelib file to Blackboard as your submission.

This homework does not have a hard deadline by itself — this gives you time flexibility to get everything working on your own computer.

However, you must become familiar with drawing schematics, icons, and layouts, and dealing with hierarchical circuits.

3. Future work

The next homework will have you use LTspice to find the propagation delays and rise/fall times of your NAND and AND gates. (and will have a deadline)

1. As in: zero points