Logical Effort technique

Tutorial about the method of Logical Effort for analyzing and designing logic circuits.

1. Logical Effort technique

The method of Logical Effort assumes a linear delay model, where the delay of a gate is predicted by some parasitic delay from self-loading and a delay term which scales linearly with the attached load capacitance.

\[\text{(delay) } d = g \cdot h + p\]

Terms

g	stage logical effort
h	stage electrical effort
p	stage parasitic delay
G	path logical effort
H	path electrical effort
P	path parasitic delay

Table 1. Summary of Logical Effort terms
Stage		Path (N stages)
Term	Name	Term	Name
\(g\)	stage logical effort	\(\displaystyle G=\prod g_i\)	path logical effort
\(h=\dfrac{C_{out}}{C_{in}}\)	stage electrical effort	\(H=\dfrac{C_{load}}{C_{in, 1}}\)	path electrical effort
\(b\)	branching effort	\(\displaystyle B=\prod b_i\)	path branch effort
\(f=g \, h\)	stage effort	\(F=G \, B \, H\)	path effort
\(f\)	stage effort delay	\(\displaystyle D_F=\sum f_i\)	path effort delay
\(p\)	stage parasitic delay	\(P=\sum p_i\)	path parasitic delay
\(d=f+p\)	stage delay	\(\begin{align} D &= \sum d_i \\ &= \sum (f_i + p_i) \\ &= D_F + P \end{align}\)	path delay

2. Stage logical effort, g

It may be a little unfortunate about the naming of this term, but it really is the core of whuzzup with the overall Logical Effort technique. To stay clear, this term as applied to an individual gate will always be carry a prefix stage logical effort, while the technique will always be capitalized.

Stage logical effort is the ratio of the input’s input capacitance to the input capacitance of an inverter with an equivalent drive strength.

\[g = \dfrac{C_{in\text{, this}}}{C_{in\text{, inv}}}\]

This definition holds for any size of gate.

3. Stage electrical effort, h

\[\begin{align} h_i &= \dfrac{C_{out}}{C_{in}} \\[1em] &= \dfrac{C_{in\text{, next}} + C_{\text{branch}}}{C_{in\text{, this}}} \end{align}\]

Recall the definition of stage effort

\[g = \dfrac{C_{in\text{, this}}}{C_{in\text{, inv}}}, \\ \Rightarrow C_{in\text{, this}} = g\, C_{inv}\]

\[\begin{align} h_i &= \dfrac{g_{\text{next}}\, C_{inv} + C_{\text{branch}}}{g_{\text{this}}\, C_{inv}} \\[1em] \end{align}\]

Let’s make an assumption that all of the branches away from the path of interest are only inputs to other gates and not any other capacitances. If that is the case, then

\[C_{\text{branch}} = \sum\limits_j k_j\, g_j\, C_{inv}\]

\(j\) selects each of the branching path’s gates,
\(k_j\) is the size of this gate with respect to a reference version having the same drive strength as the reference inverter,
\(g_j\) is the gate’s logical effort.

\[\begin{align} h_i &= \dfrac{k_{\text{next}}\, g_{\text{next}}\, C_{inv} + \sum\limits_j k_j\, g_j\, C_{inv}}{g_{\text{this}}\, C_{inv}} \\[1em] &= \dfrac{k_{\text{next}}\, g_{\text{next}} + \sum k_j\, g_j}{g_{\text{this}}} \end{align}\]

If this is a design problem, we have to stop at this point since we haven’t (yet) determined the sizes of the gates.

Remember that we are ultimately interested in the delay and are using L.E. to make this computation easier (?) and avoid (slow) simulation. The intuition gained from this process keeps us in the realm of Engineering and out of the tempting mode of Blindguessandchecking. ^[1]

1. During high school working as a summer farm hand, the farmer I worked for’s mantra was work smart. This was driven home to me the day we changed a fluid-filled tractor tire (1000+ pounds) using only hand tools in the field.