Electric schematic entry
configure for LTspice simulation

Review Electric manual Ch 1
    Nodes
        Ports where arcs (wires) connect
    Arcs
        constraints
  
    Cell - collection of nodes and arcs
        views - schematic, layout, icon, etc
        *exports* define outside connections
  
    Cell *instances* may be placed in other cells as nodes
        up/down hierarchy
    
    Library - collection of cells
        single *.jelib file on disk
    
    Complete circuit may span use several libraries
        Top-level cell contains entire circuit representation


Homework:
    Create a new library named "Lastname_inverters.jelib"
    
    Setup this library with the proper configuration as outlined in the video.

    Draw the schematic of a single, minimum-sized inverter named "inv1", use
    (W/L)p = (W/L)n = 4/2 lambda.  In our process, lambda = 300nm.
    
    Export the input and output nodes and use off-page symbols to help
    visually identify them.
    
    Create an icon for your inverter.
    
    Create another cell named "test_inv" and draw a schematic with a spice
    pulse source driving a chain of 3 instances of your "inv1" cell.  The first is a buffer for the (fake, not real-world) spice pulse, the second is your actual device-under-test (DUT), and the third acts as a realistic load for the DUT.
    
    Add extra spice directives for the power supply and model inclusion as
    discussed in the video.
    
    Perform a transient simulation with this circuit.  Measure the following
    quantities with LTspice:
        t_pLH and t_pHL delays of the middle inverter
            (HL, LH are at the output)
        t_rise and t_fall at the middle inverter's output node
        
    These times will not be symmetrical.  Copy and modify your inverter to make the delays equal using integer sizes.  Show this by simulation.
    
    Calculate the *average* delay for each of these inverters.  Create a
    third inverter which minimizes the average delay.
    
    Hint: This is a good time to learn about the ".measure" command in spice
          to automate your delay measurements instead of only using the
          waveform cursors.
    
    Hint: By the third inverter, it may be useful to stay in LTspice to
          optimize your design instead of modifying in Electric first.

    Hint: A good tool to automatically optimize parameters in a design for
          a performance metric is ASCO (A Spice Circuit Optimizer).  It has
          a version which will run in windows and use LTspice.
          http://asco.sourceforge.net/
          (these types of tools are the bomb!  First, understand how the
          circuit works and find the relevant parameters to vary, then ask
          a tool like this to do the tedious task of: vary a set of
          parameters, simulate, measure, compare, do-it-all-again)


    Turn in via email with the subject "ECE429 hw02":
        The "Lastname_inverters.jelib" library with all your designs.  There
        should be three (3) "test_*" cells, one for testing each inverter
        design.  I should be able to directly simulate these three cells
        with no additional intervention.
        
        A 1-2 page report in PDF format detailing:
            * Your three inverters, their sizing, and performance.
            * Discussion about the trade-offs involved between the "equal
              delay" and the "minimum delay" inverters.
            
            Your audience is your direct manager who is familiar with the
            terminology but not with the small details of inverter delays
            and transistor properties.  Include relevant schematics and plots
            to support your discussion.  It should not be necessary to open
            Electric to understand the homework assignment.