Due Friday, March 23 at the start of class.

(only 10% late if turned in by the start of Exam 1 on Monday)

1. Master-slave DFF schematic

Construct a positive edge triggered master-slave DFF schematic in our 0.5μm technology.  

Do this in a hierarchical manner, with cells of each sub-part.  This means:

  • Only the inverter and transmission gate cells contain transistors! For the inverter use Wp/Wn=12/6 λ, and txgate use Wp/Wn=12/6 λ.

  • The D-latch cell contains multiple inverter cells and transmission gate cells.

  • The DFF cell contains 2, D-latch cell instances.

  • The test cell contains a single DFF cell and multiple inverter cells.

    • Use 2 inverters to buffer the D input pulse source to the DFF.

    • Use 2 inverters to buffer the CLK input pulse source and generate the two clock signals for the DFF.

    • Load each of the Q and Qbar DFF outputs with 4 inverters (fan out of 4) each to simulate driving realistic loads.

  • Simulate your DFF to determine the following times:

    • Two clock-to-Q delay times (tcqHL and tcqLH).

    • Setup time (tsu).  The minimum time between D changing and the clock edge that correctly captures the D value. (Hold time is negative for this circuit, we will simulate it later)

See the video for the settings that ensure your preferences and scale factor is setup properly.

Email your ".jelib" file with the subject "ECE 429 hw10"  containing your:

  • DFF cell (sch+ic)

  • inverter cell (sch+ic)

  • transmission gate cell (sch+ic)

  • d-latch cell (sch+ic)

  • test schematic (sch)

It should be possible for me to open this library from a folder that already contains the transistor models "c5.txt", find zero DRC errors, and run an LTspice simulation of your test schematic.

→ Use the #chipdesign channel on Slack to help each other out.  The turn-in is individual, but the figuring out how to do X or Y in Electric and LTspice can be a community effort.

FYI, the next assignment will be to make a layout of your DFF and simulate it using the same test setup.