Due Friday April 4 at the start of class.

1. Hierarchical layout of a DFF

Beginning with your work from hw10, draw the layout view for your inverter and txgate cells.

Each cell needs to pass DRC (Tools  DRC  Check Hierarchically) for both {sch} and {lay} views.

cell-mirroring
Figure 1. Mirroring cells

2. Notes

MOSIS Scalable CMOS design rules (SCMOS) scmos.pdf.

The sizing scheme of using units of λ instead of absolute lengths in meters is called scalable design rules. The ON Semiconductor C5 process used for the project uses the technology code SCN3ME_SUBM with λ = 0.30 μm.

According to the scmos.pdf document, SCN3ME_SUBM decodes as

  • SCN — N-well process

  • 3M — 3 layers of metal

  • E — second layer of polysilicon (to make the second electrode of a poly-poly2 capacitor)

  • SUBM — updated rules to be compatible with typical sub-micron processes