LibreLane PM32 multiplier

Purposes for this assignment:

  • Translate the LibreLane newcomer’s tutorial to run on our OSIC system.

1. The Tutorial

Your objective is to end up with a GDSII layout of the PM32 multiplier design.

Newcomers' Tutorial - LibreLane

There are some parts that are not relevant or need modified between their instructions and how our setup works. The parts you are not required to modify yourself are:

  • Installation section

    • The OSIC system already has librelane set up.

    • You can and should do the "smoke test". BUT you need to activate the PDK for sky130A first.

The sak in sak-pdk stands for "Swiss Army Knife".

  • The Verilog files referenced are in a new folder under /foss/common. It is read-only for users but is where you have easy access to course-wide files that everyone needs.

Work the tutorial and create your configuration .json with the correct content so you end up with a GDS layout.

Use the same pin ordering and have a nearly identical layout to "Fig. 12 Custom IO placed layout"

  • Screenshot your layout being displayed, include the browser URL showing your user ID.

2. Additional questions

Electric has a Design Rule Checker (DRC) and will also show (most) violations live during manual layout, as you experienced in prior assignments. The LibreLane flow also runs DRC checks.

  1. What tools are used for the checking? and Why does LibreLane use more than one checker to do the "same thing"?

  2. What does a "DRC-clean" design/layout mean (more than "no errors"), what’s "wrong" when a DRC error is found?

Ensuring that the geometry for fabrication matches the intended "schematic" is critical for the design process — we no longer or rarely manually draw layouts on separate layers to create transistors and other electronic components. LVS (for Layout Versus Schematic) is the name for this checking process. The LVS action in LibreLane uses the software netgen.

  1. What is the "layout" and what is the "schematic" that are being compared?

  2. Find the home page for netgen. What version are you (implicitly via LibreLane) using compared to the latest release of netgen.

Quoted from the Netgen release notes: "Version 1.5.76 effectively completes the major development of netgen as a commercial-grade tool. All remaining revisions will be bug fixes or minor enhancements."

  1. When was netgen version 1.5.76 released?

  2. Why does the author consider version 1.5 "complete and competitive with commercial-grade tools" ? I wonder if there have been any improvements in LVS algorithms since the declaration.

STA is Static Timing Analysis.

  1. What is "slack" and why is a positive value good?

  2. How do "IPVT corners" affect timing slack?

Plasma Induced Gate Oxide Damage is destroying your MOSFET gate even before you finish manufacturing the wafer. It is bad and largely avoidable by following DRC rules related to minimizing the effect, called "Antenna" rules. Adding an "antenna diode cell" is the solution for the LibreLane / OpenROAD tools (there are other solutions!).

  1. Using your knowledge from prior coursework (specifically ECE 340), describe the mechanism of protection that adding an "antenna diode cell" has to keep the charge collected on a gate node from accumulating too high (thus creating too large of a voltage / E-filed to spark across the gate oxide layer, which is generally destructive).

Finally,

  1. Speculate on the number of job openings available in the VLSI / chip design industry and its relative salaries compared to other engineering fields and roles. Use economic principles such as supply and demand in your discussion. Especially compare to software roles.