1. Design project

The remainder of the work for the course is focused on your own design and getting it ready for tapeout.

All aspects of the design are to be hosted on a GitHub project which is derived from a Tiny Tapeout template for the process you are using.

  • Description of what the design does as a narrative.

  • Block diagram of the system.

  • Top level I/O pin assignments and purposes.

  • Example waveforms from its correct operation.

  • inputs vs. time

  • resulting outputs

  • Test bench scripts that drive inputs and check for correct ouptuts.

2. Submission

For this submission,

  • Update the docs/info.md of your repository to describe your project

  • Create a block diagram of the design that includes the top-level I/O pins from Tiny Tapeout and the major internal blocks required inside your project. Include the graphic as part of docs/info.md.

  • Basic setup of your top-level Verilog description and project configuration to match your top-level module name and file(s): info.yaml, test/Makefile, test/tb.v.

Submit a link to your GitHub repository.

3. Fabrication update

Tiny Tapeout has opened a second shuttle TTSKY26b which closes May 11.

Those wishing to have their design fabricated after this date will need to switch to the GF26a shuttle for a submission. That uses the GlobalFoundries 0.18UM 3.3V/(5V)6V MCU process and PDK, requiring you to switch to the corresponding template.