The Objectives listed here are minimum requirements, an individual student creates more in consultation with the instructor.

1. Overall course goals

1.1. G-FAB: Fabrication

Learn the fundamentals of the fabrication and physical design of integrated circuits.

1.2. G-LOGIC: Digital logic design

Design combinational and sequential digital logic (integrated) circuits.

1.3. G-SIM: Simulation

Simulate and characterize combinational and sequential circuits at the transistor and structural levels.

1.4. G-FLOW: Design flow

Use hierarchical tools and techniques to manage design complexity.

Bottom-up

Transistors to macro cell libraries and process design kit (PDK)

Top-town

RTL-to-GDSII using OpenLane.

1.5. G-PROJ: Project tapeout

Create a small project suitable for submission to the Efabless Open MPW Shuttle Program.

Obtain practical experience with each stage of the ASIC design flow.

2. Objectives

Each Objective has one or more Tasks whose actions support meeting the Objective.