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Review of MOSFET physics
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CMOS fabrication processes
Combinational logic design styles
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Static CMOS
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Ratioed
-
CVSL
-
Dynamic
-
Pass transistor
Sequential circuits
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Timing
-
Latches
-
Flip-Flops
-
DFF in detail
-
setup and hold constraints
-
internal delays
-
Topics
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Clock domains and synchronization
-
Metastability
-
-
Delay
-
RC model
-
Elmore
-
Logical effort
-
-
Power
-
Dynamic
-
Static
-
Energy-delay optimization
-
Low power techniques
-
-
Interconnect
-
Layout parasitics
-
Delay
-
-
Simulation using *SPICE (LTspice and Ngspice)
-
Transistor models
-
Parametric variation
-
Scripted measurements
-
Synthesis
-
Static timing analysis
-
Floorplanning
-
Placement
-
I/O
-
Power distribution network
-
Clock tree distribution
-
-
Routing
-
Parasitic extraction
-
Post-layout simulation
-
DRC
-
LVS
-
GDSII tapeout
See also OpenLane Design Stages