Generate a PWL file for SPICE

Upload a .vwf file and receive the corresponding .pwl file suitable for including in a SPICE simulation.

VWF input file format

# comments are the "#" character to the end of the line
[name=value parameters, one per line]
[space-separated column labels for voltage source names AND node names]
[one line per bit interval of 0 or 1 for each column, no spaces between]

Example .vwf contents for testing an adder:

# Two 4-bit inputs
clockdelay=500p
clockrisefall = 100p
risefall=200p
bittime=1n
bitlow=0
bithigh=5
a3 a2 a1 a0 b3 b2 b1 b0   #eight voltage sources
00000000
00010001
00010010
11111111   # comments are allowed here
01011010
01011011

... generates the following .pwl file:

Vclock clock 0 pulse(0 5 500p 1.000E-10 1.000E-10 4.5000E-10 1.0E-9)

Va3 a3 0 PWL
+ 0 0
+ 3.0000E-9 0
+ 3.2000E-9 5
+ 4.0000E-9 5
+ 4.2000E-9 0

Va2 a2 0 PWL
+ 0 0
+ 3.0000E-9 0
+ 3.2000E-9 5

Va1 a1 0 PWL
+ 0 0
+ 3.0000E-9 0
+ 3.2000E-9 5
+ 4.0000E-9 5
+ 4.2000E-9 0

Va0 a0 0 PWL
+ 0 0
+ 1.0000E-9 0
+ 1.2000E-9 5

Vb3 b3 0 PWL
+ 0 0
+ 3.0000E-9 0
+ 3.2000E-9 5

Vb2 b2 0 PWL
+ 0 0
+ 3.0000E-9 0
+ 3.2000E-9 5
+ 4.0000E-9 5
+ 4.2000E-9 0

Vb1 b1 0 PWL
+ 0 0
+ 2.0000E-9 0
+ 2.2000E-9 5

Vb0 b0 0 PWL
+ 0 0
+ 1.0000E-9 0
+ 1.2000E-9 5
+ 2.0000E-9 5
+ 2.2000E-9 0
+ 3.0000E-9 0
+ 3.2000E-9 5
+ 4.0000E-9 5
+ 4.2000E-9 0
+ 5.0000E-9 0
+ 5.2000E-9 5