This lab’s purpose is to provide hands-on practice at implementing arbitrary logic functions in the static CMOS logic circuit style. It exercises independent design and critical thinking skills in an open-ended lab procedure.

1. Introduction

CMOS logic gates can implement near-arbitrary logic functions in a single gate design. Functions that are easy to implement have non-complemented inputs and have inverting outputs. In their canonical from, these use a sum-of-products with an overall inversion. Logic functions which use inverted inputs or a non-inverted ouput are generated simply by placing additional inverters in the circuit. In this way, any logic function can be realized with a single core gate structure and extra inverters.

Because of this capability, libraries of standard cells are designed and provided by companies for building-block digital logic design on CMOS integrated circuits. Besides the normal 2 or 3-input logic gates, other functions like AND-OR-INVERT (AOI) are provided to reduce the overall implementation area. AOI gates are 3 or more input functions represented as a sum-of-products, a simple version being Y = (AB + C)'.

The construction techniques and measurements from Lab 6 - CMOS inverter will be used here also. Please refer to the previous materials for reference.

2. Experiment

Table 1. Logic functions
ABC out0 out1 out2

000

1

1

1

001

1

0

0

010

1

0

1

011

1

0

0

100

0

1

1

101

1

1

0

110

0

0

0

111

0

0

0

Parts needed:

  • BS170 n-channel MOSFETs and p-channel MOSFETs

  •  μF electrolytic capacitor for \(C_S\). “power supply bypass capacitor”

  •  nF film or ceramic capacitor (red or yellow) for \(C_{load}\). Use the same value as your Lab 6 inverter.

  • 2 oscilloscope probes

  • BNC to minigrabber cable

  • Small solderless breadboard

It may be useful to refer to the oscilloscope’s manual. A copy is posted in the Docs folder in Google Drive.

When beginning a session with your oscilloscope, always reset it back to Factory Default settings!
[ Default Setup ] → [ Factory Default ]

2.1. Design the schematic of your logic function

  1. Your group’s specific function from Table 1 will be assigned by your instructor.

  2. Find the boolean function which represents this gate.

  3. Use boolean algebra to manipulate this function to put it into the form \(out = \overline{(function)}\)

  4. Design the N-MOS pull-down network (PDN) function and schematic according to the terms under the overall inversion: \((function)\). This function is true when there is a connection between out and GND via N-MOS transistors in the ON state.

  5. Find the complementary P-MOS pull-up network (PUN) function and schematic. Begin with the PDN function, invert it, and use DeMorgan’s law to turn it into a function using \(\overline{A}\), \(\overline{B}\), \(\overline{C}\) terms. This function is true when there is a connection from Vdd to out with ON-state P-MOS transistors. Remember that a P-type transistor is ON when the gate is LOW. Input A is connected to the P-gate, corresponding to the \(\overline{A}\) term in the logic function.

    • It may be necessary to use double-bar terms, \(\overline{(\overline{A})}\). This input then needs an extra inverter to generate the inverse signal.

2.2. Verify the truth table for your schematic

This is a separate step to cross-check that the circuit represented by your schematic works properly.

On paper, apply \(0\,\mathrm{V}\) and \(5\,\mathrm{V}\) input voltages in all \(2^3 = 8\) combinations. For each input combination, determine if each transistor is ON or OFF and find the resulting output voltage. Your lab partner’s responsibility is to not just agree, but to catch errors!

2.3. Construct a CMOS inverter

Construct a CMOS inverter on a protoboard with a load capacitor \(C_{load}\) exactly like Lab 6. Be sure to always include the power supply bypass capacitor \(C_s\). Use the BS170 N-MOS and _ _ _ _ _ P-MOS transistors for all devices in your experiment.

  • Measure this reference inverter output’s \(t_{rise}\), \(t_{fall}\), \(t_{pHL}\), and \(t_{pLH}\) times.

Use 10% and 90% rise/fall time thresholds. Recall that propagation delay \(t_p\) is measured from 50% of the input to 50% of the resulting output transition. Include both \(C_{load}\) and \(C_{s}\).

2.4. Construct your logic gate

Construct your logic gate on a protoboard.[1] Use the same model of transistors as for your inverter and the same \(C_{load}\) capacitor.

  • Verify the static truth table.

  • Measure your gate’s

    • \(t_{rise}\),

    • \(t_{fall}\),

    • \(t_{pHL}\), and

    • \(t_{pLH}\) times for all transitions that involve only a single input changing.[2]

Do this by replacing one of the inputs with a signal generator or using the "single" function on the oscilloscopes and measuring the input/output waveforms as done in Lab 6.

Can you predict which input transistions will yield the best- and worst-case delay times?

2.5. Report

Collect your measurements for your inverter and all requested combinations of your gate. Each group will have a different set of measurements depending on their function. Your ultimate deliverable is to be a combination of a datasheet and a test results report.

Though you work with a partner during the lab time, the report is an individual submission.

This report has the following deliverables:

  1. Draft datasheet (Friday)

  2. Final datasheet (Start of final exam)

See Datasheet requirements for the complete information.

1. Do this in small steps, testing each part as you go. It seems slower, but greatly reduces your troubleshooting time.
2. E.g. attach A to the wavegen and set B and C to all four combinations using wires. Then move wavegen to B and test all four combinations of A and C, etc.