1. Lab goals
- Topics
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Transistor DC bias solution.
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Verify DC solution on constructed circuit.
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Amplifier AC gain table prediction, measurement, small-signal analysis, and simulation.
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- Your task
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is to match your selected common-emitter amplifier’s DC solution and small-signal mid-frequency gain obtained via:
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Measurements of a prototype build of the circuit.
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Simulation of the AC frequency response in CircuitLab and/or LTspice.
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Predictions of amplifier gain using the Bipolar transistor amplifier types table.
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Analysis from the small-signal equivalent circuit.
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- References
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Transistor datasheets may be found in the
datasheetssubfolder at: Google Drive folder: ECE 341 / docs
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2. Selected amplifier
Select one of the three amplifiers used as examples from day13.
2.1. Simplifications for small-signal analysis
- Yamaha PM-1000 Channel Equalizer Figure 1: PM-1000
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All potentiometers to middle position.
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C9, C10, C11 are very low impedance at mid-frequencies (short-circuit).
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High pass filter switch to OFF.
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For DC also:
R48to 0 Ω.
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- HF-1 Microphone Amplifier Figure 2: HF-1
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C120 is a high impedance at mid-frequencies (open-circuit).
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C121, C122, and C124 are low impedance (short).
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- Generic CE Figure 3: CE Amplifier
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Cin, Ce, and Cout are all low impedances at mid-frequencies. Select values to ensure that they have relatively little effect in the 1—10 kHz range.
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Select a DC collector current of about 2 mA.
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3. DC bias solution and setup
Because the inductance of the inductor has zero impedance at DC, the collector voltage is equal to the supply voltage (−5 V for this pnp version). This means that the base-collector junction is always reverse-biased and therefore the transistor is always in forward-active mode, regardless of the potentiometer position. Though this is a feature of an inductor-fed amplifier and a common structure in radio-frequency circuits, it is a bit of a problem for the purposes of this lab.
Therefore, we need to remove L1 from the circuit when adjusting the Rx potentiometer’s wiper position when setting the DC bias condition.
Beginning with [ce-amp], ignore (remove) both Ce and L1 and find (calculate) the values required of each end of part of the potentiometer Rtop and Rbottom that sets VOUT to within ±100 mV of 0 V.
Remember that Rtop + Rbottom = 10 kΩ.
[1]
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Build this circuit (still omitting
CeandL1). Adjust the potentiometer to yield the proper output voltage with the transistor in forward-active mode.
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There are two potentiometer positions that yield the requested VOUT, one with the transistor in forward-active mode and the other in saturation mode. How would you compute this other solution (base voltage)? |
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Measure the resulting potentiometer resistances. They should be very near what you calculated earlier. Remember to remove it from the circuit when measuring so that no other components are effectively in parallel.
Add a power supply bypass capacitor (about 0.1-1 μF). These are placed physically close to your circuit and between the power supply nodes. Use one if using a single +10 V supply. If using dual ±5 V supplies, place one capacitor between +5 V and the reference node and a second between the reference node and -5 V.
Construct the DC equivalent version of this schematic (all capacitors open-circuits) in CircuitLab or LTspice and verify that your computed DC voltages match a DC simulation (.op in LTspice).
4. AC measurements
Before measuring and simulating, find the frequencies where the reactive components Ce and L1 have a significant effect.
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At what frequency does the magnitude of the impedance of
Ce, \(\left|\dfrac{1}{j\,2\pi f\, C_e}\right|\), equal that ofR4? Above this frequency, the ________ impedance “wins” while below this frequency, the ________ impedance “wins” the parallel combination. -
At what frequency does the magnitude of the impedance of
L1, \(|j\,2 \pi f\, L_1|\), equal that ofR5? Above this frequency, the ________ impedance “wins” while below this frequency, the ________ impedance “wins” the parallel combination.
Remember these frequencies when looking at the amplifier’s frequency response.
| You can use your AD2 to measure this frequency response! It is the Network tool, which shows the transfer function of the circuit. |
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Measure the signal gain vout / vin at frequencies of 100 Hz, 1 kHz, 10 kHz, 100 kHz, and 1 MHz.
Add capacitor Ce to the circuit and verify that the DC bias point remains the same.
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Again, measure the signal gain vout / vin at frequencies of 100 Hz, 1 kHz, 10 kHz, 100 kHz, and 1 MHz.
Add inductor L1.
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Measure the resulting DC bias point. Does the collector current stay the same? What about VOUT (DC)? Does this make sense?
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Finally, measure the signal gain vout / vin at frequencies of 100 Hz, 1 kHz, 10 kHz, 100 kHz, and 1 MHz.
5. Documentation
Refer back to the Lab goals.
Create a document which includes five sections, four of which correspond to the “Your task:” items. This will form your submission for dbm03
5.1. Section 1 - DC analysis / simulation / measurements
Show your work which finds the values of Rtop and Rbottom for the potentiometer Rx that sets the output voltage to half-way between the power supply voltages.
This was 0 V, or, if you are using the lower power supply as the measurement reference (V−) then it was 5 V.
Include your measurements of the potentiometer position that sets this output voltage. Remember that only one of the two possible positions has the transistor in forward-active mode, the other puts the transistor in saturation mode.
Build the circuit in a circuit simulator (CircuitLab is ideal for this) and use it to also find the DC values of
A natural way to show the results is to draw the schematic and add two sets of node voltage annotations. One set is from your hand calculations and the other is your measured values. A table of node names and voltages is also fine, but less helpful to look at.