1. Tasks
1.1. SPICE clock
Define a SPICE (using LTspice) voltage source for generating clock waveforms.
-
Low/high levels of 0 and 5 V
-
50 MHz clock rate
-
50% duty cycle
-
10-90% and 90-10% rise and fall times of 1 ns
Document and report:
-
the type and parameters of the voltage source
-
a transient simulation of appropriate duration
-
simulation data plot with measured annotations showing that the waveform meets the specifications
1.2. Inverter DC characteristic
Draw a schematic of a static CMOS inverter in LTspice to simulate its DC characteristics.
Use the model and parameters of the 0.5 μm process with λ=0.3 μm c5.txt.
-
Power supply VDD = 5 V
-
NMOS transistor W/L = 10λ / 2λ
Determine the width of the PMOS transistor a static CMOS required yield a switching point of \(V_{DD}/2\) (where \(V_{out}=V_{in}\)). Do this by two methods:
-
Circuit analysis using the long-channel drain current equations. (set IDP = IDN with both transistors in saturation mode)
-
DC sweep simulation using the c5.txt transistor models with LTspice.
| The PMOS widths will be slightly different between these two results. |
1.3. Inverter transient characteristics
Begin from your LTspice schematic of a single CMOS inverter.
Expand the circuit to include 5 copies of the inverter and connected as shown, each using the same transistor sizes as determined from the DC sweep simulation.
Use the clock created in the first task to drive the first inverter.
| Each transistor must be given realistic source and drain areas and perimeter dimensions for the transistor parameters. |
From a transient simulation, measure the following parameters:
-
tpLH : propagation delay from
x1tox2whenx2is rising -
tpHL : propagation delay from
x1tox2whenx2is falling -
trise : 10% to 90% rise time of node
x2 -
tfall : 90% to 10% fall time of node
x2
Report:
-
the process and results from determining the source and drain area and perimeter values
-
the measured times with a brief report on how they were measured